Changes between Version 5 and Version 6 of WARPLab/HardwareConfiguration/WARPv2
- Timestamp:
- Dec 30, 2014, 2:08:19 AM (9 years ago)
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WARPLab/HardwareConfiguration/WARPv2
v5 v6 16 16 The [wiki:HardwareUsersGuides/FPGABoard_v2.2/OtherIO#DigitalIO debug header] is configured by default to map to the following pins: 17 17 18 [[Image(Debug_Header_ Diagram_BnW.png)]]18 [[Image(Debug_Header_Connections.png)]] 19 19 20 '''NOTE:''' The Debug Header is defined in the system.ucf and the connections are defined in the system.mhs 21 22 * The Trigger output and Trigger input pins above are used with the [wiki:WARPLab/Reference/TriggerManager Trigger Manager] 20 23 21 24 === Clock Configuration ===