[[TracNav(WARPLab/TOC)]] = WARPLab Reference Design Hardware Config: WARP v2 = [[Image(WARP_v2_labelled.jpg,width=400)]] === Radio Interface === * In the 2 RF Node configuration (ie only RF A and RF B are populated), you should only use the '''2RF bitstream''' in the [wiki:WARPLab/Downloads download]. * In the 4 RF Node configuration (ie all RF interfaces are populated), you should only use the '''4RF bitstream''' in the [wiki:WARPLab/Downloads download]. === Debug Header === ''Updated for WARPLab 7.5.1''' The [wiki:HardwareUsersGuides/FPGABoard_v2.2/OtherIO#DigitalIO debug header] is configured by default to map to the following pins: [[Image(Debug_Header_Diagram.png)]] [[Image(Debug_Header_Connections.png)]] '''NOTE:''' The Debug Header is defined in the system.ucf and the connections are defined in the system.mhs * The Trigger output and Trigger input pins above are used with the [wiki:WARPLab/Reference/TriggerManager Trigger Manager] === Clock Configuration === The WARPLab reference design does not require any external clock connections. By default the reference design will use the oscillators on the WARP v2 board for all system and RF clocking. The reference design does support both sourcing and sinking external clocks for synchronization of multiple nodes. The WARP v2 kit must be equipped with a [wiki:HardwareUsersGuides/ClockBoard_v1.1 clock board] to source/sink clocks. * Detailed information on the WARP v2 Clocking configuration can be found [wiki:HardwareUsersGuides/FPGABoard_v2.2/Clocking here]. * Detailed information on the WARP v2 Clock Board can be found [wiki:HardwareUsersGuides/ClockBoard_v1.1 here]. The WARPLab Reference Design assumes the Clock and Radio Boards are connected according to the specs in the [wiki:howto/connectclocks Clock Connection howto]. === Ethernet === * Only one Ethernet connection (Eth A) on the board * Please note that due to hardware limitations within Xilinx peripherals, WARP v2 only supports non-jumbo Ethernet frames up to 1514 bytes.