= WARPLab Revision History = = This is an archive of previous releases of the WARPLab 6 reference design. Please use the [wiki:WARPLab latest WARPLab design]. = ---- == '''Notes for v6.5''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= Arch =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v3 || 6.5 || 26-Feb-2013 || 13.4 || MB/PLB || [http://warp.rice.edu/dl/refdes/warplab/v6.5/bit/w3_WARPLab_v6p5_2rf.bit w3_WARPLab_v6p5_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.5/bit/w3_WARPLab_v6p5_2rf.bin w3_WARPLab_v6p5_2rf.bin][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.5/edk/w3_WARPLab_ReferenceDesign_v6p5_2rf.zip w3_WARPLab_ReferenceDesign_v6p5_2rf.zip] || [http://warp.rice.edu/dl/refdes/warplab/v6.5/bit/w3_WARPLab_v6p5_4rf.bit w3_WARPLab_v6p5_4rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.5/bit/w3_WARPLab_v6p5_4rf.bin w3_WARPLab_v6p5_4rf.bin][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.5/edk/w3_WARPLab_ReferenceDesign_v6p5_4rf.zip w3_WARPLab_ReferenceDesign_v6p5_4rf.zip] || v3: * added support for MM-MMCX == '''Notes for v6.4''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= Arch =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v3 || 6.3b || 15-Jan-2013 || 13.4 || MB/PLB || - || [http://warp.rice.edu/dl/refdes/warplab/v6.4/bit/w3_WARPLab_v6p4_4rf.bit w3_WARPLab_v6p4_4rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.4/bit/w3_WARPLab_v6p4_4rf.bin w3_WARPLab_v6p4_4rf.bin][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.4/edk/w3_WARPLab_ReferenceDesign_v6p4_4rf.zip w3_WARPLab_ReferenceDesign_v6p4_4rf.zip] || v3: * added support for FMC-2RF-2X245 in 4-radio design. This release is otherwise compatible with the 6.3 M-code == '''Notes for v6.3''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= Arch =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v3 || 6.3b || 10-Dec-2012 || 13.4 || MB/PLB || [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w3_WARPLab_v6p3b_2rf.bit w3_WARPLab_v6p3b_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w3_WARPLab_v6p3b_2rf.bin w3_WARPLab_v6p3b_2rf.bin][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/edk/w3_WARPLab_ReferenceDesign_v6p3b_2rf.zip w3_WARPLab_ReferenceDesign_v6p3b_2rf.zip] || - || || WARP v2 || 6.3 || 20-Nov-2012 || 13.4 || PPC/PLB || [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w2_WARPLab_v6p3_2rf.bit w2_WARPLab_v6p3_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w2_WARPLab_v6p3_2rf.ace w2_WARPLab_v6p3_2rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/edk/w2_WARPLab_ReferenceDesign_v6p3_2rf.zip w2_WARPLab_ReferenceDesign_v6p3_2rf.zip] || [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w2_WARPLab_v6p3_4rf.bit w2_WARPLab_v6p3_4rf.bit][[BR]][http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w2_WARPLab_v6p3_4rf.ace w2_WARPLab_v6p3_4rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/edk/w2_WARPLab_ReferenceDesign_v6p3_4rf.zip w2_WARPLab_ReferenceDesign_v6p3_4rf.zip] || || WARP v1 || 6.3 || 20-Nov-2012 || 10.1.03 || PPC/PLB || [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w1_WARPLab_v6p3_2rf.bit w1_WARPLab_v6p3_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w1_WARPLab_v6p3_2rf.ace w1_WARPLab_v6p3_2rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/edk/w1_WARPLab_ReferenceDesign_v6p3_2rf.zip w1_WARPLab_ReferenceDesign_v6p3_2rf.zip] || [http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w1_WARPLab_v6p3_4rf.bit w1_WARPLab_v6p3_4rf.bit][[BR]][http://warp.rice.edu/dl/refdes/warplab/v6.3/bit/w1_WARPLab_v6p3_4rf.ace w1_WARPLab_v6p3_4rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.3/edk/w1_WARPLab_ReferenceDesign_v6p3_4rf.zip w1_WARPLab_ReferenceDesign_v6p3_4rf.zip] || v3: * 6.3b: Fixed important bug in the C-code controlling receiver's high pass filter * Swapped LSB/MSB for DIP switch, so LSB is right-most switch * Updated Ethernet constraints for ETH_A MDIO signals v2: * Added boot-time configuration of clocks using the DIP switch on Radio 2 * Fixed bug in UCF that set the wrong IO standard on debug pins (should be LVTTL) v1: * No changes. C-code modified to report the new version number. This release is just to stay in lock step with v2/v3. == '''Notes for v6.2''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v3 || 6.2 || 29-Aug-2012 || 13.4 || [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w3_WARPLab_v6p2_2rf.bit w3_WARPLab_v6p2_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w3_WARPLab_v6p2_2rf.bin w3_WARPLab_v6p2_2rf.bin][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/edk/w3_WARPLab_ReferenceDesign_v6p2_2rf.zip w3_WARPLab_ReferenceDesign_v6p2_2rf.zip] || - || || WARP v2 || 6.2 || 11-Sep-2012 || 13.4 || [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w2_WARPLab_v6p2_2rf.bit w2_WARPLab_v6p2_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w2_WARPLab_v6p2_2rf.ace w2_WARPLab_v6p2_2rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/edk/w2_WARPLab_ReferenceDesign_v6p2_2rf.zip w2_WARPLab_ReferenceDesign_v6p2_2rf.zip] || [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w2_WARPLab_v6p2_4rf.bit w2_WARPLab_v6p2_4rf.bit][[BR]][http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w2_WARPLab_v6p2_4rf.ace w2_WARPLab_v6p2_4rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/edk/w2_WARPLab_ReferenceDesign_v6p2_4rf.zip w2_WARPLab_ReferenceDesign_v6p2_4rf.zip] || || WARP v1 || 6.2 || 6-Sep-2012 || 10.1.03 || [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w1_WARPLab_v6p2_2rf.bit w1_WARPLab_v6p2_2rf.bit][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w1_WARPLab_v6p2_2rf.ace w1_WARPLab_v6p2_2rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/edk/w1_WARPLab_ReferenceDesign_v6p2_2rf.zip w1_WARPLab_ReferenceDesign_v6p2_2rf.zip] || [http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w1_WARPLab_v6p2_4rf.bit w1_WARPLab_v6p2_4rf.bit][[BR]][http://warp.rice.edu/dl/refdes/warplab/v6.2/bit/w1_WARPLab_v6p2_4rf.ace w1_WARPLab_v6p2_4rf.ace][[BR]] [http://warp.rice.edu/dl/refdes/warplab/v6.2/edk/w1_WARPLab_ReferenceDesign_v6p2_4rf.zip w1_WARPLab_ReferenceDesign_v6p2_4rf.zip] || * Added support for [http://www.mangocomm.com/products/kits/warp-v3-kit WARP v3]. In this release, the source models and software for WARPLab are different for WARP v3 than the v1 and v2 hardware. In a future release, these will merge back together to a common code base. * Added a new WARPLab command to verify network settings from within Matlab. If it even seems like WARPLab isn't working, simply run warplab_networkCheck(N) from the Matlab command line (where N is the number of nodes in your setup). This will run a series of diagnoses to help figure out what the problem is. * We introduced a bug in the prior 6.1 release that made the processing of sync packets jittery. This has been fixed in this release. == '''Notes for v6.1''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v2 || 6.1 || Jul-2012 || 13.4 || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_2x2_v06_01_FPGAv2.bit?rev=1761 WARPLab_2x2_v06_01_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_2x2_v06_01_FPGAv2.ace?rev=1761 WARPLab_2x2_v06_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip] || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_4x4_v06_01_FPGAv2.bit?rev=1761 WARPLab_4x4_v06_01_FPGAv2.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_4x4_v06_01_FPGAv2.ace?rev=1761 WARPLab_4x4_v06_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_01_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_01_FPGAv2.zip] || || WARP v1 || 6.1 || Jul-2012 || 10.1.03 || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_2x2_v06_01_FPGAv1.bit?rev=1761 WARPLab_2x2_v06_01_FPGAv1.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_2x2_v06_01_FPGAv1.ace?rev=1761 WARPLab_2x2_v06_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip] || [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_4x4_v06_01_FPGAv1.bit?rev=1761 WARPLab_4x4_v06_01_FPGAv1.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_4x4_v06_01_FPGAv1.ace?rev=1761 WARPLab_4x4_v06_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_01_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_01_FPGAv1.zip] || * Small, but important, bug fix. MAC addresses for each node were not updated based on dip switch value. This made any setup larger than 1 node fail due to arp table collisions. This has been resolved. v6.0 is deprecated and should not be used == '''Notes for v6.0''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v2 || 6.0 || Jul-2012 || 13.4 || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv2.bit WARPLab_2x2_v06_00_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv2.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip] || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv2.bit WARPLab_4x4_v06_00_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv2.ace WARPLab_4x4_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip] || || WARP v1 || 6.0 || Jul-2012 || 10.1.03 || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv1.bit WARPLab_2x2_v06_00_FPGAv1.bit][[BR]] [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv1.ace WARPLab_2x2_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip] || [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv1.bit WARPLab_4x4_v06_00_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv1.ace WARPLab_4x4_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip] || * Design defaults to using gigabit Ethernet on WARP v2 Hardware (Virtex-4) * Improved packet handling on WARP v2 for fewer packet drops * Sync packets now sent as proper broadcast IP frames (X.X.X.255). Manual ARP table entries for sync packets no longer necessary. * Small change to M-code reference to reduce likelihood of "failed to receive ACK" error. * Thanks to a modified pnet for Matlab's UDP handling, WARPLab is sped by ~10x == '''Notes for v5.2''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v2 || 5.2 || Dec-2009 || 10.1.03 || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_2x2_v05_02_FPGAv2.bit WARPLab_2x2_v05_02_FPGAv2.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_2x2_v05_02_FPGAv2.ace WARPLab_2x2_v05_02_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip] || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_4x4_v05_02_FPGAv2.bit WARPLab_4x4_v05_02_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_4x4_v05_02_FPGAv2.ace WARPLab_4x4_v05_02_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip] || || WARP v1 || 5.2 || Dec-2009 || 10.1.03 || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_2x2_v05_02_FPGAv1.bit WARPLab_2x2_v05_02_FPGAv1.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_2x2_v05_02_FPGAv1.ace WARPLab_2x2_v05_02_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v05_02_FPGAv1.zip] || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_4x4_v05_02_FPGAv1.bit WARPLab_4x4_v05_02_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_4x4_v05_02_FPGAv1.ace WARPLab_4x4_v05_02_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v05_02_FPGAv1.zip] || * Can store RSSI data in the 4x4 design * Consolidated the Sysgen models. Now there is one Sysgen model, {{{warplab_mimo_4x4.mdl}}}, that implements the full system: 4 radios with I/Q and RSSI buffers. The 2x2 MIMO and 4x4 MIMO [wiki:WARPLab/RefDesign Reference Designs] are identical except the 2x2 Design leaves two paths of the model unconnected. * Minor update: Added the Null MGT wrapper core to the project (see note at the end of the [wiki:HardwareUsersGuides/FPGABoard_v2.2/MGTs FPGA Board user guide]) == '''Notes for v5.1''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v2 || 5.2 || Nov-2009 || 10.1.03 || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_2x2_v05_01_FPGAv2.bit WARPLab_2x2_v05_01_FPGAv2.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_2x2_v05_01_FPGAv2.ace WARPLab_2x2_v05_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_01_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v05_01_FPGAv2.zip] || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_4x4_v05_01_FPGAv2.bit WARPLab_4x4_v05_01_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_4x4_v05_01_FPGAv2.ace WARPLab_4x4_v05_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_01_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v05_01_FPGAv2.zip] || || WARP v1 || 5.2 || Nov-2009 || 10.1.03 || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_2x2_v05_01_FPGAv1.bit WARPLab_2x2_v05_01_FPGAv1.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_2x2_v05_01_FPGAv1.ace WARPLab_2x2_v05_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_01_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v05_01_FPGAv1.zip] || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_4x4_v05_01_FPGAv1.bit WARPLab_4x4_v05_01_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_4x4_v05_01_FPGAv1.ace WARPLab_4x4_v05_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_01_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v05_01_FPGAv1.zip] || * Builds upon the features of Version 5 * Support for both Version 1 and 2 of the FPGA Board * Single C-code base for both the 2x2 and 4x4 Reference Designs * Interoperable across both versions of the FPGA Boards == '''Notes for v5.0''' == ||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =|| || WARP v1 || 5.2 || Sep-2009 || 10.1.03 || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_MIMO2x2_MIMO4x4_R05/warplab_mimo_2x2_v05.bit warplab_mimo_2x2_v05.bit][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_MIMO_2x2_ReferenceDesign_xps_v05.zip WARPLab_MIMO_2x2_ReferenceDesign_xps_v05.zip] || [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_MIMO2x2_MIMO4x4_R05/warplab_mimo_4x4_v05.bit warplab_mimo_4x4_v05.bit][[BR]][http://warp.rice.edu/bigFiles/WARPLab_MIMO_4x4_ReferenceDesign_xps_v05.zip WARPLab_MIMO_4x4_ReferenceDesign_xps_v05.zip] || * Includes Automatic Gain Control (AGC). Previous versions of WARPLab required Manual Gain Control (MGC), the user was required to set receiver gains manually. Now AGC or MGC can be selected by M-code functions. * RSSI data read is supported by the 2x2 MIMO bitstream but not by the 4x4 MIMO bitstream * Continuous transmission mode is supported by both the 2x2 and 4x4 bitstreams