136 | | The configuration values are stored in the WARP v3 EEPROM starting at byte address 15000. Configuration values are stored as 2-byte address/data pairs, with each pair corresponding to a 1-byte register write via SPI to a single device. There are separate configuration values for the 3 SPI slave devices (the RF reference clock buffer, the sampling clock buffer and the PLL on the CM-PLL clock module). Multiple configurations can be defined for each device to support run-time selection of the active configuration via the clock module switches. |
137 | | |
138 | | The EEPROM addresses for the various clock configuration values are listed in the table below. |
| 136 | The configuration values are stored in the WARP v3 EEPROM starting at byte address 15000. Configuration values are stored as 2-byte address/data pairs, with each pair corresponding to a 1-byte register write via SPI to a single device. There are separate configuration values for the 3 SPI slave devices (the RF reference clock buffer, the sampling clock buffer and the PLL on the CM-PLL clock module). Multiple configurations can be defined for each device to support run-time selection of the active configuration via the clock module switches. The mapping of clock module switch settings to selected EEPROM configuration is the same as the mapping described above. |
| 137 | |
| 138 | Configuration values in the EEPROM are stored as pairs of address/data bytes. Each address/data pair specifies a single register write via SPI. Each address byte must be a valid register address for the selected device. The corresponding data byte must be a valid value for the selected register. The w3_clock_controller_axi core does not implement any validation in the register addresses or values. Invalid configuration values in the EEPROM will result in invalid configurations in hardware. |
| 139 | |
| 140 | The EEPROM addresses for the various clock configuration values are listed in the table below. A sample application to write configuration values to the EEPROM is available in [browser:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/util/clk_cfg_eeprom_writer.c clk_cfg_eeprom_writer.c]. This example application encodes the same default register settings as the internal configuration values used by the HDL for non-EEPROM configuration. |