Changes between Version 21 and Version 22 of cores/w3_clock_controller
- Timestamp:
- Jun 29, 2015, 9:12:42 AM (9 years ago)
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cores/w3_clock_controller
v21 v22 22 22 1. Selecting (and possibly configuring) the clock source for the sampling clock buffer 23 23 24 These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnect ed, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits.24 These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnect, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits. 25 25 26 26 The w3_clock_controller_axi HDL also supports run-time selection of various clock configurations using the switches on the CM-PLL and CM-MMCX clock modules. The core implements 7 configurations by default:
