wiki:cores/w3_clock_controller_old

WARP v3 Clock Controller (w3_clock_controller)

This core implements an SPI master for reading/writing registers in the AD9512 clock buffers on the WARP v3 board. For details about how these buffers are connected to the FPGA and RF interfaces, refer to the WARP v3 User Guide Clocking section.

The w3_clock_controller core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4.

Hardware

The WARP v3 board uses two AD9512 clock buffers: one for distributing the sampling clock (to the RF interfaces, FPGA and FMC slot) and one for distributing the RF reference clock (to the RF interfaces and FMC slot). The w3_clock_controller HDL implements parallel SPI interfaces, one per AD9512 buffer. There are 4 SPI pins per buffer which must be connected to the corresponding FPGA pins. Refer to the WARP v3 reference projects for examples of known-good hardware configurations.

Driver

The w3_clock_controller pcore includes a C driver to facilitate control of the AD9512s from user code. Refer to the w3_clock_controller driver documentation for more details.

All driver functions require the base memory address of the w3_clock_controller pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the xparameters.h file when you generate a BSP. The auto-generated macro should be named XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR (assuming your pcore instance is named w3_CLOCK_controller_0, as in our reference projects).

//Define our own macro, in case EDK changes its naming scheme in the future
// Assumes pcore instance is named w3_ad_controller_0; confirm in xparameters.h
#define CLOCK_BASEADDR XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR

Sampling Clock Source

Many user designs for WARP v3 use the sampling clock reference as the master clock for FPGA logic. Our WARP v3 Template Projects do this, for example. One implication of this approach is the sampling clock source must be stable before the FPGA logic attempts to use it. When the on-board clock is used, this is straightforward. When an off-board clock source is used (via a Clock Module) the FPGA logic must be held in reset until the sampling clock buffer can switch to the external cock source.

The w3_clock_controller contains a small block to handle this "at boot" clock selection. Immediately after the FPGA is configured this block writes a handful of registers in the sampling clock buffer to configure the sampling clock input. The block asserts an "invalid" output to hold the rest of the FPGA design in reset until its register writes are complete. The "at boot" logic uses the 200MHz oscillator on WARP v3, which is always available (even when the rest of the FPGA design uses an off-board clock).

The w3_clock_controller at boot logic uses the two switches on the CM-MMCX to select the clock mode. When both switches are down (logic 0) the off-board sampling clock will be selected. All other switch settings will use the on-board sampling clock. User software can interpret the other switch states as desired (i.e. to select on/off board RF reference clock, to en/disable CM-MMCX clock outputs, etc.).

Usage

An important factor in configuring the WARP v3 clock buffers is whether the FPGA logic implementing the w3_clock_controller core is itself clocked by the sampling clock. If so, it is critical the properties of the AD9512->FPGA clock are not changed by user code at run-time. All other outputs from the AD9512 buffers can be changed as needed by user code.

The w3_clock_controller driver provides functions to configure the AD9512 output dividers, thereby configuring the frequency of the clocks feeding the RF interface AD9963 chips (the ADC/DAC chips). It is critical that the AD9512->AD9963 clock frequency be consistent with all other rates in the FPGA->DAC and ADC->FPGA interfaces. The combination of AD9963 clock settings (DLL state, ADC/DAC clock source, etc.), AD9963 filter settings (interpolation/decimation rates), AD9512 dividers and internal FPGA->w3_ad_bridge clock connections must all agree. Refer to the WARP v3 User Guide RF section for more details and examples of valid AD9512/AD9963/FPGA configurations.

The MHS snippet below shows a typical use of the w3_clock_controller (taken from the OnBoardPeriphs template project).

BEGIN w3_clock_controller
 PARAMETER INSTANCE = w3_clock_controller_0
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_BASEADDR = 0xc0400000
 PARAMETER C_HIGHADDR = 0xc040ffff
 BUS_INTERFACE SPLB = plb_primary
#AD9512 SPI pins
 PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
 PORT samp_spi_cs_n = clk_samp_spi_cs_n
 PORT samp_spi_mosi = clk_samp_spi_mosi
 PORT rfref_spi_mosi = clk_rfref_spi_mosi
 PORT samp_spi_sclk = clk_samp_spi_sclk
 PORT rfref_spi_sclk = clk_rfref_spi_sclk
 PORT samp_spi_miso = clk_samp_spi_miso
 PORT rfref_spi_miso = clk_rfref_spi_miso
#At boot ports
 PORT at_boot_clk_in = clk_200MHz #always-running clock
 PORT at_boot_clk_in_valid = clk_gen_1_locked #valid indicator for at_boot_clk_in (when sourced from MMCM)
 PORT at_boot_config_sw = cm_mmcx_sw #CM-MMCX SIP switches
 PORT at_boot_clkbuf_clocks_invalid = mmcm_inputs_invalid #reset output
#Software-readable input for user applications
 PORT usr_status = net_gnd
END

Source

The full hardware and software source code is available in the repository: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_b. The VHDL, Verilog and C source code are made available under the WARP license.

Last modified 7 years ago Last modified on Jan 28, 2015, 3:45:09 PM