| 1 | = WARP v3 IIC EEPROM Master (w3_iic_eeprom) = |
| 2 | |
| 3 | This core implements an IIC master for accessing the IIC EEPROM on the WARP v3 board. The core provides a PLBv46 slave interface for control from user code. |
| 4 | |
| 5 | == Hardware == |
| 6 | |
| 7 | The w3_iic_eeprom core is packaged as a pcore which can instantiated in an XPS project. The HDL has been tested in hardware using ISE / XPS 13.4. |
| 8 | |
| 9 | The MHS snippet below shows the w3_iic_eeprom instantiation used in the WARP v3 reference projects. Note that the top-level port name and internal net names are identical. This is a requirement imposed by XPS for connecting the tri-state IIC signals. |
| 10 | |
| 11 | {{{ |
| 12 | #!sh |
| 13 | |
| 14 | #Top level ports |
| 15 | ... |
| 16 | # IIC EEPROM pins |
| 17 | PORT IIC_EEPROM_iic_scl_pin = IIC_EEPROM_iic_scl_pin, DIR = IO |
| 18 | PORT IIC_EEPROM_iic_sda_pin = IIC_EEPROM_iic_sda_pin, DIR = IO |
| 19 | ... |
| 20 | BEGIN w3_iic_eeprom |
| 21 | PARAMETER INSTANCE = w3_iic_eeprom_0 |
| 22 | PARAMETER HW_VER = 1.00.b |
| 23 | PARAMETER C_BASEADDR = 0xcbe00000 |
| 24 | PARAMETER C_HIGHADDR = 0xcbe0ffff |
| 25 | BUS_INTERFACE SPLB = plb_primary |
| 26 | PORT iic_scl = IIC_EEPROM_iic_scl_pin |
| 27 | PORT iic_sda = IIC_EEPROM_iic_sda_pin |
| 28 | END |
| 29 | ... |
| 30 | }}} |
| 31 | |
| 32 | == Driver == |
| 33 | |
| 34 | The w3_iic_eeprom pcore includes a driver to facilitate accessing the EEPROM from user code. A simple example of using the driver is given below. Refer to the [export:/PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b/doc/html/api/index.html w3_iic_eeprom driver documentation] for more details. |
| 35 | |
| 36 | All driver functions require the base memory address of the w3_iic_eeprom pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the {{{xparameters.h}}} file when you generate a BSP. The auto-generated macro should be named {{{XPAR_W3_IIC_EEPROM_0_BASEADDR}}} (assuming your pcore instance is named {{{w3_iic_eeprom_0}}}, as in the example above). |
| 37 | |
| 38 | {{{ |
| 39 | #!C |
| 40 | //Define our own macro, in case EDK changes its naming scheme in the future |
| 41 | // Assumes pcore instance is named w3_iic_eeprom_0; confirm in xparameters.h |
| 42 | #define EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_0_BASEADDR |
| 43 | |
| 44 | int x; |
| 45 | u32 board_sn; |
| 46 | |
| 47 | //Initialize the EEPROM controller at boot |
| 48 | iic_eeprom_init(EEPROM_BASEADDR, 0x64); |
| 49 | |
| 50 | //Write a value to the EEPROM (set EEPROM byte address 2345 to 182) |
| 51 | x = iic_eeprom_writeByte(EEPROM_BASEADDR, 2345, 182); |
| 52 | if(x != 0) xil_printf("EEPROM Write Error!\n"); |
| 53 | |
| 54 | //Read the value back from EEPROM |
| 55 | x = iic_eeprom_readByte(EEPROM_BASEADDR, 2345); |
| 56 | if(x != 182) xil_printf("EEPROM Read Error (read %d, should be 182)!\n", x); |
| 57 | |
| 58 | //Read the WARP v3 board serial number from the EEPROM |
| 59 | board_sn = w3_eeprom_readSerialNum(EEPROM_BASEADDDR); |
| 60 | xil_printf("Board s/n: W3-a-%05d\n", board_sn); |
| 61 | }}} |
| 62 | |
| 63 | |
| 64 | == Source == |
| 65 | |