WARP v3: SPI Flash

The WARP v3 board includes a 128Mb SPI flash memory tied to the configuration interface of the Virtex-6 FPGA. This flash memory can store a bitstream which will be automatically loaded into the FPGA on powerup. For more details on the hardware, refer to the WARP v3 User Guide.

Using the SPI flash for configuration requires 4 steps:

  1. Select the SPI flash for configuration via the config DIP switch
  2. Preparing your .bit file for conversion
  3. Convert your .bit file to a .mcs file
  4. Program the SPI flash with your .mcs file

These processes are detailed below.

These instructions have been tested with Xilinx ISE 13.4.

Selecting the SPI Flash

Set the left-most switch in the configuration DIP switch to 1. Refer to the WARP v3 User Guide for details.

Preparing the .bit file

The FPGA uses Master SPI mode when loading a bitstream from the SPI flash. In this mode the FPGA generates the configuration clock signal and drives it to the CCLK pin. The CCLK pin is routed to the SPI serial clock input. A faster CCLK will result in a faster configuration process.

The CCLK frequency is specified in the .bit file and is preserved when generating the .mcs file (as described above). You can change the CCLK frequency via the -g ConfigRate bitgen option. We have successfully tested CCLK frequencies up to 33MHz. Higher frequencies will sometimes work. However the FPGA-generated CCLK frequency is specified as ±55%, so higher nominal frequencies may violate the SPI flash max frequency of 54MHz.

To set the CCLK frequency to 33MHz:

  • ISE: open the Generate Programming File properties and change Configuration Options -> ConfigRate to 33.
  • XPS: edit Project -> bitgen.ut, add a line:
    -g ConfigRate:33

If you're using the SDK, you must update and re-export the bitstream from XPS for the ConfigRate to take effect.

All the WARP reference and template designs are configured for ConfigRate of 33MHz by default.

Creating the .mcs File

You must convert your .bit file to a .mcs file before it can be written to the SPI flash. There are two methods for this: the iMPACT GUI or on the command line with promgen.

To generate the PROM programming file via the iMPACT GUI:

  1. Open iMPACT and start the Create PROM File flow
  2. In the PROM File Formatter window:
    1. Set Storage Target to SPI Flash -> Configure Single FPGA
    2. Click the first green arrow
    3. Set Storage Device to 128M
    4. Click Add Storage Device, then click the second green arrow
    5. Change the Output File Name and Output File Location to your preferred path
    6. Set File Format to MCS and Add Non-Configuration Data Files to No
    7. Click OK
  3. Click OK in the Add Device dialog box
  4. Select your desired FPGA configuration .bit file
  5. Click No when prompted to add another device file, then click OK to continue
  6. Right-click in the iMPACT window and choose Generate File

To generate the PROM programming file via promgen:

  1. Launch a Xilinx command prompt
  2. Navigate to the folder with your .bit file
  3. Run:
    promgen -spi -p mcs -c FF -s 131072 -u 0 <your .bit file name> -o <new .mcs file name>

Programming the SPI Flash

You must use iMPACT to program the SPI flash. This flash programming process employs a Xilinx-provided FPGA design which connects the FPGA's JTAG port with the SPI flash pins. As a result, running this process re-configures the Virtex-6 FPGA, losing whatever configuration may be loaded.

To write the .mcs file to the SPI flash:

  1. Connect a programming cable to the FPGA JTAG connector (J14)
  2. Run iMPACT (if not already open) and start the Boundary Scan flow
  3. Right-click and choose Initialize Chain
  4. Click OK in the Device Programming Properties window
  5. Right-click on the FPGA icon and select Add BPI/SPI Flash
  6. Select your .mcs file
  7. The Select Attached SPI/BPI window will show. Choose SPI PROM model M25P128, data width 1.
  8. Right-click on the Flash icon (not the FPGA icon) and choose Program
  9. Confirm Design-Specific Erase Before Programming is checked
  10. Optionally un-check Verify; verification increases the programming time, and we've never seen a verification error
  11. Click OK

iMPACT will now begin writing your .mcs file to the SPI flash. This process is slow, typically lasting 5+ minutes (yes, minutes; we have no idea why Xilinx's implementation of JTAG->SPI is so slow). Watch the iMPACT GUI and console for status and error messages.

When the programming process completes the FPGA will initiate a configuration cycle from the flash. You will see the green STAT LED glow at half intensity as the FPGA reads the configuration file. The LED will illuminate fully when configuration completes.

Last modified 12 years ago Last modified on Aug 25, 2012, 11:20:12 PM