Changes between Version 2 and Version 3 of ppc_prog_overview/ppc405_arch

Timestamp:

Aug 3, 2006, 1:59:26 PM (18 years ago)

Author:

sgupta

Comment:

--

ppc_prog_overview/ppc405_arch

@@ -6 +6 @@
 ((Insert Reference Diagram 1)) [[BR]]
 
-The PowerPC control spreads out in a tree-like fashion within the FPGA. The core, itself, connects to the Instruction and Data On-Chip-Memory controllers, which then interface with the FPGA Block RAM. The core is also directly attached to two busses: The CoreConnect Device Control Register (DCR) Bus, and the CoreConnect Processor Local Bus (PLB). The CoreConnect interface is a bus protocol developed by IBM.[[BR]]
+The PowerPC control spreads out in a tree-like fashion within the FPGA. The core, itself, connects to the Instruction and Data On-Chip-Memory controllers, which then interface with the FPGA Block RAM. The core is also directly attached to two busses: The !CoreConnect Device Control Register (DCR) Bus, and the !CoreConnect Processor Local Bus (PLB). The !CoreConnect interface is a bus protocol developed by IBM.[[BR]]
 From [http://www.xilinx.com/ipcenter/processor_central/coreconnect/coreconnect_dcr.htm Xilinx]: [[BR]]
 {{{
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 }}}
 
-The PLB Bus is 64bits-wide and designed to interface with peripherals that require high-speed priority access to the core, such as memory controller-type peripherals. Slower peripherals, such as general-purpose-input-output (GPIO) devices, can connect to the CoreConnect On-Chip Peripheral Bus (OPB). The OPB interfaces with the PLB using a PLB-OPB Bridge peripheral for control.  
+The PLB Bus is 64bits-wide and designed to interface with peripherals that require high-speed priority access to the core, such as memory controller-type peripherals. Slower peripherals, such as general-purpose-input-output (GPIO) devices, can connect to the !CoreConnect On-Chip Peripheral Bus (OPB). The OPB interfaces with the PLB using a PLB-OPB Bridge peripheral for control.  
 
 == The PowerPC 405 Architecture ==
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 The CPU uses a 5-stage instruction pipeline. It has 32 32bit general purposes registers and hardware multipliers and adders. The Execute unit can support all 32bit PowerPC UISA integer instructions. There is no hardware support for floating-point operations, but they may be implemented in software.[[BR]]       [[BR]]
 The Memory Management Unit (MMU) can support up to 4GB of address space and allows for variable page sizes. It also features software control over page-replacement method used. Page sizes can be between 1KB and 16MB.[[BR]][[BR]]
-The debug resources allow the PowerPC to be read and controlled (tracing/event triggering). Debugging operations are done through registers, which can be accessed by software or a JTAG interface. Using the JTAG interface, registers can be read and written using XMD, or more advanced control over the PowerPC can be achieved by using ChipScope.[[BR]][[BR]]
+The debug resources allow the PowerPC to be read and controlled (tracing/event triggering). Debugging operations are done through registers, which can be accessed by software or a JTAG interface. Using the JTAG interface, registers can be read and written using XMD, or more advanced control over the PowerPC can be achieved by using !ChipScope.[[BR]][[BR]]
 The timing mechanism in the PowerPC has a 64bit time base, which three types of timers are able to draw upon – the Programming Interval Timer (PIT), the Fixed Interval Timer (FIT), and the Watchdog Timer (WDT). The PIT is a 32bit countdown timer, which causes an interrupt when its count reaches zero. The FIT causes a binary interrupt when a user-chosen bit in the 64bit time base changes from a 0 to a 1. There four pre-defined bits that may be user may choose from. The WDT has the same functionality as the FIT, but instead of causing an interrupt when a chosen 0 to 1 bit transition occurs, the WDT causes a hardware reset. The user may customize the type of reset that occurs. Timer API and information can be found in the IP Catalog of XPS, under the “Timer” section.[[BR]]
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