| | 1 | == sysgen2opb Shared Memory Extension Dual Port RAM Requirements == |
| | 2 | Since all input addresses need to be UFix14_0, All DPRAM blocks will need to have a depth of 2^(14) |
| | 3 | === DPRAM (Read only) === |
| | 4 | |
| | 5 | DPRAM Name Prefix: SMRO_ |
| | 6 | |
| | 7 | __DPRAM Inport addrb Source Block__ |
| | 8 | [[BR]]Name Prefix: SMROAddr_ |
| | 9 | [[BR]]Block Type: Gateway In |
| | 10 | [[BR]]Output Type: UFix14_0 |
| | 11 | |
| | 12 | __DPRAM Inport dinb Source Block__ |
| | 13 | [[BR]]Name Prefix: SMRODataI_ |
| | 14 | [[BR]]Block Type: Xilinx Constant |
| | 15 | [[BR]]Constant Value: 0 |
| | 16 | [[BR]]Number of bits: 32 |
| | 17 | |
| | 18 | __DPRAM Inport web Source Block__ |
| | 19 | [[BR]]Name Prefix: SMROWE_ |
| | 20 | [[BR]]Block Type: Xilinx Constant |
| | 21 | [[BR]]Output Type: Boolean |
| | 22 | [[BR]]Constant Value: 0 |
| | 23 | |
| | 24 | __DPRAM Outport B Destination Block__ |
| | 25 | [[BR]]Name Prefix: SMRODataO_ |
| | 26 | [[BR]]Block Type: Gateway Out |
| | 27 | |
| | 28 | === DPRAM (Write only) === |
| | 29 | |
| | 30 | DPRAM Name Prefix: SMWO_ |
| | 31 | |
| | 32 | __DPRAM Inport addrb Source Block__ |
| | 33 | [[BR]]Name Prefix: SMWOAddr_ |
| | 34 | [[BR]]Block Type: Gateway In |
| | 35 | [[BR]]Output Type: UFix14_0 |
| | 36 | |
| | 37 | __DPRAM Inport dinb Source Block__ |
| | 38 | [[BR]]Name Prefix: SMWODataI_ |
| | 39 | [[BR]]Block Type: Gateway In |
| | 40 | [[BR]]Number of bits: 32 |
| | 41 | |
| | 42 | __DPRAM Inport web Source Block__ |
| | 43 | [[BR]]Name Prefix: SMWOWE_ |
| | 44 | [[BR]]Block Type: Gateway In |
| | 45 | [[BR]]Output Type: Boolean |
| | 46 | |
| | 47 | __DPRAM Outport B Destination Block__ |
| | 48 | [[BR]]There's no need to connect anything to Outport B due to the fact that the Shared Memory is being written |
