{{{
#!div class=important style="border: 2pt solid; text-align: center"
'''Note''': As of version 10.1.02, Xilinx has added a stable EDK export flow to System Generator. The new flow creates a PLB46 slave interface with access to registers, FIFOs and shared memory blocks in the user design. This flow completely replaces sysgen2opb and the OPB Export Tool. As a result, these tools are no longer maintained.
}}}
= sysgen2opb Shared Memory Extension Dual Port RAM Requirements =
Invoke the shared memory extenion with the argument 'smon' when calling sysgen2opb:

{{{
>> sysgen2opb('myModel', 'smon')
}}}

In order to use this extension, your model must contain at least one dual-port RAM configured as described below.

== DPRAM (Read only) ==
[[Image(WARPImages:SMRO_dpram.png)]]

DPRAM Name Prefix: SMRO_

__DPRAM Inport addrb Source Block__
[[BR]]Name Prefix: SMROAddr_
[[BR]]Block Type: Gateway In
[[BR]]Output Type: UFix14_0

__DPRAM Inport dinb Source Block__
[[BR]]Name Prefix: SMRODataI_
[[BR]]Block Type: Xilinx Constant
[[BR]]Constant Value: 0
[[BR]]Number of bits: 32

__DPRAM Inport web Source Block__
[[BR]]Name Prefix: SMROWE_
[[BR]]Block Type: Xilinx Constant
[[BR]]Output Type: Boolean
[[BR]]Constant Value: 0

__DPRAM Outport B Destination Block__
[[BR]]Name Prefix: SMRODataO_
[[BR]]Block Type: Gateway Out



== DPRAM (Write only) ==
[[Image(WARPImages:SMWO_dpram.png)]]

DPRAM Name Prefix: SMWO_

__DPRAM Inport addrb Source Block__
[[BR]]Name Prefix: SMWOAddr_
[[BR]]Block Type: Gateway In
[[BR]]Output Type: UFix14_0

__DPRAM Inport dinb Source Block__
[[BR]]Name Prefix: SMWODataI_
[[BR]]Block Type: Gateway In
[[BR]]Number of bits: 32

__DPRAM Inport web Source Block__
[[BR]]Name Prefix: SMWOWE_
[[BR]]Block Type: Gateway In
[[BR]]Output Type: Boolean

__DPRAM Outport B Destination Block__
[[BR]]There's no need to connect anything to Outport B due to the fact that the Shared Memory is being written