Version 2 (modified by elliotng, 18 years ago) (diff) |
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sysgen2opb Shared Memory Extension Dual Port RAM Requirements
Since all input addresses need to be UFix14_0, All DPRAM blocks will need to have a depth of 2(14)
DPRAM (Read only)
DPRAM Name Prefix: SMRO_
DPRAM Inport addrb Source Block
Name Prefix: SMROAddr_
Block Type: Gateway In
Output Type: UFix14_0
DPRAM Inport dinb Source Block
Name Prefix: SMRODataI_
Block Type: Xilinx Constant
Constant Value: 0
Number of bits: 32
DPRAM Inport web Source Block
Name Prefix: SMROWE_
Block Type: Xilinx Constant
Output Type: Boolean
Constant Value: 0
DPRAM Outport B Destination Block
Name Prefix: SMRODataO_
Block Type: Gateway Out
DPRAM (Write only)
DPRAM Name Prefix: SMWO_
DPRAM Inport addrb Source Block
Name Prefix: SMWOAddr_
Block Type: Gateway In
Output Type: UFix14_0
DPRAM Inport dinb Source Block
Name Prefix: SMWODataI_
Block Type: Gateway In
Number of bits: 32
DPRAM Inport web Source Block
Name Prefix: SMWOWE_
Block Type: Gateway In
Output Type: Boolean
DPRAM Outport B Destination Block
There's no need to connect anything to Outport B due to the fact that the Shared Memory is being written