= sysgen2opb Shared Memory Extension Dual Port RAM Requirements =
Since all input addresses need to be UFix14_0, All DPRAM blocks will need to have a depth of 2^(14) 
=== DPRAM (Read only) ===
[[Image(WARPImages:SMRO_dpram.png, align=center, 450)]]

DPRAM Name Prefix: SMRO_

__DPRAM Inport addrb Source Block__
[[BR]]Name Prefix: SMROAddr_
[[BR]]Block Type: Gateway In
[[BR]]Output Type: UFix14_0

__DPRAM Inport dinb Source Block__
[[BR]]Name Prefix: SMRODataI_
[[BR]]Block Type: Xilinx Constant
[[BR]]Constant Value: 0
[[BR]]Number of bits: 32

__DPRAM Inport web Source Block__
[[BR]]Name Prefix: SMROWE_
[[BR]]Block Type: Xilinx Constant
[[BR]]Output Type: Boolean
[[BR]]Constant Value: 0

__DPRAM Outport B Destination Block__
[[BR]]Name Prefix: SMRODataO_
[[BR]]Block Type: Gateway Out

=== DPRAM (Write only) ===

DPRAM Name Prefix: SMWO_

__DPRAM Inport addrb Source Block__
[[BR]]Name Prefix: SMWOAddr_
[[BR]]Block Type: Gateway In
[[BR]]Output Type: UFix14_0

__DPRAM Inport dinb Source Block__
[[BR]]Name Prefix: SMWODataI_
[[BR]]Block Type: Gateway In
[[BR]]Number of bits: 32

__DPRAM Inport web Source Block__
[[BR]]Name Prefix: SMWOWE_
[[BR]]Block Type: Gateway In
[[BR]]Output Type: Boolean

__DPRAM Outport B Destination Block__
[[BR]]There's no need to connect anything to Outport B due to the fact that the Shared Memory is being written