Changes between Version 36 and Version 37 of sysgen2opb

Timestamp:

Jun 16, 2006, 4:48:53 PM (18 years ago)

Author:

elliotng

Comment:

--

sysgen2opb

@@ -24 +24 @@
 
 == sysgenGWSM2opb Dual Port Requirements == 
-<B><U>DPRAM (Read only)</B></U>
+'''DPRAM (Read only)'''
 
 DPRAM Name Prefix: SMRO_
 
-<U>DPRAM Inport addrb Source Block</U>
+__DPRAM Inport addrb Source Block__
 Name Prefix: SMROAddr_
 Block Type: Gateway In
 Output Type: UFix14_0
 
-<U>DPRAM Inport dinb Source Block</U>
+__DPRAM Inport dinb Source Block__
 Name Prefix: SMROWE_
 Block Type: Xilinx Constant
@@ -39 +39 @@
 Number of bits: 32
 
-<U>DPRAM Inport web Source Block</U>
+__DPRAM Inport web Source Block__
 Name Prefix: SMRODataI_
 Block Type: Xilinx Constant
@@ -45 +45 @@
 Constant Value: 0
 
-<U>DPRAM Outport B Destination Block</U>
+__DPRAM Outport B Destination Block__
 Name Prefix: SMRODataO_
 Block Type: Gateway Out
 
-<B><U>DPRAM (Write only)</B></U>
+'''DPRAM (Write only)'''
 
 DPRAM Name Prefix: SMWO_
 
-<U>DPRAM Inport addrb Source Block</U>
+__DPRAM Inport addrb Source Block__
 Name Prefix: SMWOAddr_
 Block Type: Gateway In
 Output Type: UFix14_0
 
-<U>DPRAM Inport dinb Source Block</U>
+__DPRAM Inport dinb Source Block__
 Name Prefix: SMWOWE_
 Block Type: any Xilinx blocks that can set the output number of bits to 32
 Number of bits: 32
 
-<U>DPRAM Inport web Source Block</U>
+__DPRAM Inport web Source Block__
 Name Prefix: SMWODataI_
 Block Type: Gateway In
 Output Type: Boolean
 
-<U>DPRAM Outport B Destination Block</U>
+__DPRAM Outport B Destination Block__
 Name Prefix: SMWODataO_
 Block Type: Gateway Out