Changes between Version 37 and Version 38 of sysgen2opb


Ignore:
Timestamp:
Jun 16, 2006, 4:52:31 PM (18 years ago)
Author:
elliotng
Comment:

--

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Unmodified
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  • sysgen2opb

    v37 v38  
    2424
    2525== sysgenGWSM2opb Dual Port Requirements ==
    26 '''DPRAM (Read only)'''
     26=== DPRAM (Read only) ===
    2727
    2828DPRAM Name Prefix: SMRO_
    2929
    3030__DPRAM Inport addrb Source Block__
    31 Name Prefix: SMROAddr_
    32 Block Type: Gateway In
    33 Output Type: UFix14_0
     31[[BR]]Name Prefix: SMROAddr_
     32[[BR]]Block Type: Gateway In
     33[[BR]]Output Type: UFix14_0
    3434
    3535__DPRAM Inport dinb Source Block__
    36 Name Prefix: SMROWE_
    37 Block Type: Xilinx Constant
    38 Constant Value: 0
    39 Number of bits: 32
     36[[BR]]Name Prefix: SMROWE_
     37[[BR]]Block Type: Xilinx Constant
     38[[BR]]Constant Value: 0
     39[[BR]]Number of bits: 32
    4040
    4141__DPRAM Inport web Source Block__
    42 Name Prefix: SMRODataI_
    43 Block Type: Xilinx Constant
    44 Output Type: Boolean
    45 Constant Value: 0
     42[[BR]]Name Prefix: SMRODataI_
     43[[BR]]Block Type: Xilinx Constant
     44[[BR]]Output Type: Boolean
     45[[BR]]Constant Value: 0
    4646
    4747__DPRAM Outport B Destination Block__
    48 Name Prefix: SMRODataO_
    49 Block Type: Gateway Out
     48[[BR]]Name Prefix: SMRODataO_
     49[[BR]]Block Type: Gateway Out
    5050
    51 '''DPRAM (Write only)'''
     51=== DPRAM (Write only) ===
    5252
    5353DPRAM Name Prefix: SMWO_
    5454
    5555__DPRAM Inport addrb Source Block__
    56 Name Prefix: SMWOAddr_
    57 Block Type: Gateway In
    58 Output Type: UFix14_0
     56[[BR]]Name Prefix: SMWOAddr_
     57[[BR]]Block Type: Gateway In
     58[[BR]]Output Type: UFix14_0
    5959
    6060__DPRAM Inport dinb Source Block__
    61 Name Prefix: SMWOWE_
    62 Block Type: any Xilinx blocks that can set the output number of bits to 32
    63 Number of bits: 32
     61[[BR]]Name Prefix: SMWOWE_
     62[[BR]]Block Type: any Xilinx blocks that can set the output number of bits to 32
     63[[BR]]Number of bits: 32
    6464
    6565__DPRAM Inport web Source Block__
    66 Name Prefix: SMWODataI_
    67 Block Type: Gateway In
    68 Output Type: Boolean
     66[[BR]]Name Prefix: SMWODataI_
     67[[BR]]Block Type: Gateway In
     68[[BR]]Output Type: Boolean
    6969
    7070__DPRAM Outport B Destination Block__
    71 Name Prefix: SMWODataO_
    72 Block Type: Gateway Out
     71[[BR]]Name Prefix: SMWODataO_
     72[[BR]]Block Type: Gateway Out
    7373
    7474