Changes between Version 66 and Version 67 of sysgen2opb


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Timestamp:
Jul 21, 2006, 2:03:34 PM (18 years ago)
Author:
elliotng
Comment:

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  • sysgen2opb

    v66 v67  
    1010Example unconverted and converted models are available [source:/PlatformSupport/sysgen2opb/examples here]. `orig` refers to original script example files. `smro` refers to Shared Memory read only example files. `smwo` refers to Shared Memory write only example files. 'confsubsys' refers to Configurable Subsystem Extension script example files.
    1111
    12 A full [source:Documentation/sysgen2opb%20Reference%20Design/ documentation] is available.
     12A [source:Documentation/sysgen2opb%20Reference%20Design/ full documentation] is available.
    1313
    1414== Using sysgen2opb ==
    … …  
    2929      `sysgen2opb('yourModelName', hex2dec('yourBaseAddress'), 'yourSelection')`
    3030
     31== General Guides ==
     32[wiki:sysgen2opb/GeneralDesignFlow General Design Flow]
     33[wiki:sysgen2opb/SharedMemory Shared Memory]
    3134
    32 == sysgen2opb Shared Memory Extension Dual Port RAM Requirements ==
    33 Since all input addresses need to be UFix14_0, All DPRAM blocks will need to have a depth of 2^(14)
    34 === DPRAM (Read only) ===
    3535
    36 DPRAM Name Prefix: SMRO_
    3736
    38 __DPRAM Inport addrb Source Block__
    39 [[BR]]Name Prefix: SMROAddr_
    40 [[BR]]Block Type: Gateway In
    41 [[BR]]Output Type: UFix14_0
    42 
    43 __DPRAM Inport dinb Source Block__
    44 [[BR]]Name Prefix: SMRODataI_
    45 [[BR]]Block Type: Xilinx Constant
    46 [[BR]]Constant Value: 0
    47 [[BR]]Number of bits: 32
    48 
    49 __DPRAM Inport web Source Block__
    50 [[BR]]Name Prefix: SMROWE_
    51 [[BR]]Block Type: Xilinx Constant
    52 [[BR]]Output Type: Boolean
    53 [[BR]]Constant Value: 0
    54 
    55 __DPRAM Outport B Destination Block__
    56 [[BR]]Name Prefix: SMRODataO_
    57 [[BR]]Block Type: Gateway Out
    58 
    59 === DPRAM (Write only) ===
    60 
    61 DPRAM Name Prefix: SMWO_
    62 
    63 __DPRAM Inport addrb Source Block__
    64 [[BR]]Name Prefix: SMWOAddr_
    65 [[BR]]Block Type: Gateway In
    66 [[BR]]Output Type: UFix14_0
    67 
    68 __DPRAM Inport dinb Source Block__
    69 [[BR]]Name Prefix: SMWODataI_
    70 [[BR]]Block Type: Gateway In
    71 [[BR]]Number of bits: 32
    72 
    73 __DPRAM Inport web Source Block__
    74 [[BR]]Name Prefix: SMWOWE_
    75 [[BR]]Block Type: Gateway In
    76 [[BR]]Output Type: Boolean
    77 
    78 __DPRAM Outport B Destination Block__
    79 [[BR]]There's no need to connect anything to Outport B due to the fact that the Shared Memory is being written
    8037
    8138== Using System Generator ==