Changes between Version 92 and Version 93 of sysgen2opb
- Timestamp:
- Aug 19, 2008, 10:39:37 PM (16 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
sysgen2opb
v92 v93 1 {{{ 2 #!div class=important style="border: 2pt solid; text-align: center" 3 '''Note''': As of version 10.1.02, Xilinx has added a stable EDK export flow to System Generator. The new flow creates a PLB46 slave interface with access to registers, FIFOs and shared memory blocks in the user design. This flow completely replaces sysgen2opb and the OPB Export Tool. As a result, these tools are no longer maintained. 4 }}} 5 1 6 = sysgen2opb Peripheral Conversion Tool = 2 7 'sysgen2opb' is a MATLAB script which converts a model built in [http://xilinx.com/system_generator Xilinx System Generator] into an OPB-compliant peripheral for use with the FPGA's embedded PowerPCs. The script replaces all the model's From/To Registers with memory mapped registers. It also creates the necessary address decode logic and a C header file with the resulting register map. This script is loosly based on Xilinx's application note [http://direct.xilinx.com/bvdocs/appnotes/xapp264.pdf xapp264].