sysgen2opb Peripheral Conversion Tool

This is a MATLAB script which converts a model built in Xilinx System Generator into an OPB-compliant peripheral for use with the embedded PowerPCs. The script replaces all the model's gateways in/out with memory mapped registers. It also creates the necessary address decode logic and a C header file with the resulting register map.

The latest copy of this tool is available in the repository.

Using sysgen2opb

1. Prepend "no_reg_" to a gateway's name to prevent its being converted to a register. These gateways will become top-level HDL ports in the exported peripheral.
2. Copy the script (sysgen2opb.m) and skelton peripheral model (skeleton_periph_model.mdl) to the same directory as your model.
3. More Steps Here
4. Run sysgen2opb('yourModelName', hex2dec('yourBaseAddress')) in MATLAB if you do not want to have prefixes for gateways that are not converted to registers. Otherwise, if you want prefixes, run sysgen2opb('yourModelName', hex2dec('yourBaseAddress'), 'prefix') in Matlab. Replace yourModelName with your Simulink model's name without the .mdl extension. Replace yourBaseAddress with a 32-bit memory address in hexidecimal notation. FF100000 is usually a safe choice. Replace prefix with the prefix name that you wish to have for the gateways that are not converted to registers.

Current Limitations

• The script (sysgen2opb.m) and skelton peripheral model (skeleton_periph_model.mdl) must in the same directory as the model you wish to convert.
• The model you're converting must contian at least one Gateway In and one Gateway Out which will become registers.
• The names of subsystems which contain gateways converted to registers must not contain spaces. The gateways themselves can have spaces in their names, however.
• Gateways in masked subsystems will not be converted, regardless of their name. Use ports to bring the gateways out of the masked subsystem before converting the model.
• The base address and memory size of the resulting OPB peripheral cannot be changed dynamically in XPS. These parameters must be entered manually in XPS and locked before autogenerating addresses for other peripherals.
• All gateways which become registers must be clocked at the system sample period.
• The initial values for all created registers are 0, regardless of data type or which sources drove the original gateways.
• Any sources driving gateways which are converted to registers will remain in the model. Functionally this is fine; they're just clutter.
• Gateways which become registers must be oriented Input->Output left-to-right. Rotated Gateways will still be replaced, but the Goto/From blocks used to maintain connectivity after conversion will not properly connect. Any such gateways need to be rotated/reconnected manually.
• Every register created by the script will have a unique address on a 4-byte boundary (i.e. addr[1:0]=2'b0 for all).
• Every register will be read/write. Read/write-only must be enforced by software.
• A maximum of 32 registers can be created (a limitation of the multiplexor block).
• The memory interface blocks created by the script will be placed in the middle of the top-level of the model, probably underneath existing subsystems. Connectivity won't be changed, but you'll have to clean things up by hand.