wiki:sysgen2opb

Version 64 (modified by elliotng, 18 years ago) (diff)

--

sysgen2opb Peripheral Conversion Tool

'sysgen2opb' is a MATLAB script which converts a model built in Xilinx System Generator into an OPB-compliant peripheral for use with the embedded PowerPCs. The script replaces all the model's gateways in/out with memory mapped registers. It also creates the necessary address decode logic and a C header file with the resulting register map. There are three options in running the script:

  1. Original Script - This script is exactly what is described on the above.
  2. Shared Memory Extension Script - This script is the Original Script with the Shared Memory extension. The Shared Memory support requires the usage of Dual Port RAM's.
  3. Configurable Subsystem Extension Script - This script is the Original Script with the Configurable Subsystem Extension. It will take the gateway's and register's and store them into a library of Configurable Subsystems.

The latest copy of this tool is available in the repository. You will also need a copy of Xilinx's OPB Export tool to use the models generated by sysgen2opb.

Example unconverted and converted models are available here. orig refers to original script example files. smro refers to Shared Memory read only example files. smwo refers to Shared Memory write only example files. 'confsubsys' refers to Configurable Subsystem Extension script example files.

A full documentation is available.

Using sysgen2opb

  1. Prepend "no_reg_" to a gateway's name to prevent its being converted to a register. These gateways will become top-level HDL ports in the exported peripheral.
  2. The original script is supported for System Generator version 7.1 and 8.1. The Shared Memory Extension Script and the Configurable Subsystem Extension Script are only supported for System Generator version 8.1.
  3. Copy the conversion script (sysgen2opb.m) and its required skelton peripheral model (skeleton_periph_model.mdl) to the same directory as your model.
  4. Make sure MATLAB's current working directory is the folder containing your model, the sysgen2opb script and skeleton model. Run the script on the MATLAB command line like sysgen2opb('yourModelName', hex2dec('yourBaseAddress'), 'yourSelection', 'newPrefix').
    1. Replace 'yourModelName' with your Simulink model's name without the .mdl extension.
    2. Replace 'yourBaseAddress' with a 32-bit memory address in hexidecimal notation. FF100000 is usually a safe choice.
    3. Replace 'yourSelection' with one of the following:
      1. 'orig' which will run the Original Script
      2. 'sm' which will run the Shared Memory Extension Script
      3. 'confsubsys' which will run the Configurable Subsystem Extension Script
    4. Replace 'newPrefix' with a string which will replace the "no_reg_" prefix attached to unconverted gateways.
    5. If you want to run the original script with a blank string to strip away the "no_reg_" prefix, run: sysgen2opb('yourModelName', hex2dec('yourBaseAddress'))
    6. If you want to run one of the scripts with a blank strip to strip away the "no_reg_" prefix, run: sysgen2opb('yourModelName', hex2dec('yourBaseAddress'), 'yourSelection')

sysgen2opb Shared Memory Extension Dual Port RAM Requirements

Since all input addresses need to be UFix14_0, All DPRAM blocks will need to have a depth of 2(14)

DPRAM (Read only)

DPRAM Name Prefix: SMRO_

DPRAM Inport addrb Source Block
Name Prefix: SMROAddr_
Block Type: Gateway In
Output Type: UFix14_0

DPRAM Inport dinb Source Block
Name Prefix: SMRODataI_
Block Type: Xilinx Constant
Constant Value: 0
Number of bits: 32

DPRAM Inport web Source Block
Name Prefix: SMROWE_
Block Type: Xilinx Constant
Output Type: Boolean
Constant Value: 0

DPRAM Outport B Destination Block
Name Prefix: SMRODataO_
Block Type: Gateway Out

DPRAM (Write only)

DPRAM Name Prefix: SMWO_

DPRAM Inport addrb Source Block
Name Prefix: SMWOAddr_
Block Type: Gateway In
Output Type: UFix14_0

DPRAM Inport dinb Source Block
Name Prefix: SMWODataI_
Block Type: Gateway In
Number of bits: 32

DPRAM Inport web Source Block
Name Prefix: SMWOWE_
Block Type: Gateway In
Output Type: Boolean

DPRAM Outport B Destination Block
There's no need to connect anything to Outport B due to the fact that the Shared Memory is being written

Using System Generator

When you run System Generator in order to convert it to HDL, if you use Settings to navigate to your XPS project, it will directly store the pcores folder in the XPS project directory. The pcores folder will include a 'mdlsrc' folder within the OPB folder in order to store the converted and unconverted models. It will also generate a drivers folder where the header file will be stored in the XPS project directory. In that case, you can just use #include "modelName_gateways.h" where modelName is the name of the model. This will allow you to access the different registers and shared memory variables. Otherwise, if you do not use settings, within the generated netlist folder, there will be the pcores folder and the drver folder. Be sure to bring those over to XPS once your project is created.

Current Limitations

  • The script (sysgen2opb.m) and skeleton peripheral model (skeleton_periph_model.mdl) must in the same directory as the model you wish to convert.
  • The model you're converting must contain at least one Gateway In and one Gateway Out which will become registers.
  • The base address and memory size of the resulting OPB peripheral cannot be changed dynamically in XPS. These parameters must be entered manually in XPS and locked before autogenerating addresses for other peripherals.
  • All gateways which become registers must be clocked at the system sample period.
  • Any sources driving gateways which are converted to registers will remain in the model. Functionally this is fine; they're just clutter.
  • Every register created by the script will have a unique address on a 4-byte boundary (i.e. addr[1:0]=2'b0 for all).
  • Every register will be read/write. Read/write-only must be enforced by software.
  • From the script, we can have at most 1024 Gateways. However, with some limitation in one of the tools, we can only use 450 Gateways. A check is implemented to make sure that we have less than/equal 450 Gateways.
  • The memory interface blocks created by the script will be placed in the middle of the top-level of the model, probably underneath existing subsystems. Connectivity won't be changed, but you'll have to clean things up by hand.
  • Any Boolean type connected to a Gateway Out needs to be cast to a UFix1_0 before being connected to the Gateway Out.
  • Path to output register must contain synchronous path.

Current Bugs

  • The script fails if there are no gateways or if there are no gateways out. It should fail only if there are no gateways at all.