sysgen2opb Peripheral Conversion Tool

'sysgen2opb' is a MATLAB script which converts a model built in Xilinx System Generator into an OPB-compliant peripheral for use with the embedded PowerPCs. The script replaces all the model's From/To Registers with memory mapped registers. It also creates the necessary address decode logic and a C header file with the resulting register map.

Alternatively, if an addressable dual-port storage block is used within a System Generator model, the storage element may be mapped directly into the OPB memory space. This functionality, termed the Shared Memory Extension, permits higher throughput when accessing shared storage elements. This extension can be turned on/off. This extension requires the usage of Dual Port RAM's.

The latest copy of this tool is available in the repository.

A copy of Xilinx's OPB Export tool is needed to use the models generated by sysgen2opb.

Requirements

• Xilinx System Generator 8.1, 8.2 or 9.1
• WARP OPB Export Tool
• WARP MATLAB Toolbox in MATLAB's path

Installing WARP MATLAB Toolbox

• Download or SVN checkout everything from this repository directory
• Copy it to C:\<MATLAB_DIR>\toolbox\WARP (where <MATLAB_DIR> is the root of your MATLAB installation)
• Add C:\<MATLAB_DIR>\toolbox\WARP and its subdirectories to MATLAB's path

Using sysgen2opb

1. Change MATLAB's current working directory to the folder containing your model
2. Close your model
3. On the MATLAB command line, run sysgen2opb('modelName')
4. Your model should now be ready to be generated by the OPB Export Tool.

Examples

• Intro to sysgen2opb​ Lab Exercise (from WARP Workshops)

Current sysgen2opb Extensions

• Shared Memory

Current Limitations

• The model you're converting must contain at least one RW Register and one RO Register.
• The generated OPB interface must be clocked at the system sample period.
• Every register created by the script will have a unique address on a 4-byte boundary (i.e. addr[1:0]=2'b0 for all).
• The memory interface blocks created by the script will be placed in the middle of the top-level of the model, probably underneath existing subsystems. Connectivity won't be changed, but you'll have to clean things up by hand.
• RO Registers do not support Boolean datatypes. You must cast signals to UFix1_0 before connecting the RO Register block.
• Every path to a RO Register must contain synchronous elements (i.e. no purely combinational outputs).