Last change
on this file was
1733,
checked in by murphpo, 12 years ago
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Updated PHY model with two fec_decoder black boxes and sim mux to select between them for sim/implementation. Also added script for generating simulation-only verilog for fec_decoder. All this is workaround for MATLAB crashing during simulation due to a bug in isim/Sysgen 13.4 that's under investigation by Xilinx.
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File size:
1.6 KB
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1 | bb_simgen.bat |
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2 | |
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3 | You only need to use this script if you make changes to the FEC decoder Verilog source code. |
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4 | |
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5 | This script is part of a workaround for a bug in System Generator 13.3/13.4 that causes a |
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6 | MATLAB crash during simulation of the PHY model. The crash is somehow triggered by the HDL |
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7 | simulation of the FEC decoder. Replacing the source HDL with a NGC->Verilog netlist bypasses the crash. |
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8 | |
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9 | This script implements two steps: |
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10 | 1) Generates an NGC netlist for fec_decoder_top.v/fec_decoder_rest.v |
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11 | 2) Converts the new NGC netlist into a Verilog netlist for simulation |
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12 | |
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13 | The netlist generated by this script should be used only in simulation. The original Verilog |
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14 | source should be used when generating a pcore. The latest PHY model includes a simulation |
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15 | multiplexer to automate this, using fec_decoder_top.v for implementation and fec_decoder_simOnly.v |
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16 | for simulation. |
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17 | |
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18 | Usage: |
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19 | 1) Copy your modified Verilog files, this script and its associated files (*bat *prj *opt) to a new directory. |
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20 | |
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21 | 2) Launch a Xilinx shell and cd to that directory. |
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22 | |
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23 | 3) Run 'bb_simgen.bat'; the script will run for a few minutes and generate a bunch of intermediate files/folders. |
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24 | |
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25 | 4) Copy the new Verilog file (fec_decoder_simOnly.v) to the PHY directory, replacing the existing file. |
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26 | |
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27 | 5) Copy your modified source HDL (fec_decoder_top.v / fec_decoder_rest.v) to the PHY directory, replacing the existing files. |
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28 | |
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29 | 6) If you changed any ports in the HDL you must update BOTH _config.m scripts for the Sysgen black boxes and |
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30 | update the corresponding wires/ports in the Sysgen model |
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31 | |
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32 | |
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33 | Special thanks to Brian Wiec at Xilinx for figuring out this workaround for the Sysgen crash. |
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