Changes between Version 24 and Version 25 of HardwareUsersGuides/FPGABoard_v2.2/MGTs


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Timestamp:
Oct 8, 2009, 2:03:23 PM (15 years ago)
Author:
murphpo
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  • HardwareUsersGuides/FPGABoard_v2.2/MGTs

    v24 v25  
    22
    33== WARP FPGA Board MGTs ==
     4The Virtex-4 FPGA is equipped with 10 pairs of differential multi-gigabit transceivers. Each MGT is a full-duplex transceiver supporting serial data rates up to 6.5 Gbps. The WARP FPGA board includes 8 MGT interfaces: 4 HSSDC2, 2 SATA and 2 SFP.
    45
    5 The Virtex-4 FPGA is equipped with 10 pairs of differential multi-gigabit transceivers. The MGTs can support data rates of up to 6.5 Gbps including standards such as SATA, gigabit Ethernet and Infiniband. Each of these requires a different clock speed for best performance. On the FPGA Board three different connectors have been provided: SATA host and target, HSSDC2 jacks and SFP modules.
     6The MGTs on the Virtex-4 FPGA are internally organized in two columns. Each column has two clock inputs and all the MGTs in the column can use either of those clocks. Our design maximizes the functionality by allowing the user to select the clock frequency that is input to the columns.
    67
    7 The MGTs on the FPGA are organized in two columns. Each column has two clock inputs and all the MGTs in the column can use either of those clocks. Our design maximizes the functionality by allowing the user to select the clock frequency that is input to the columns.
    8 
    9 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Loc_Front.jpg)]]
    10 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Loc_Back.jpg)]]
     8[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Loc_Front.jpg)]] [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Loc_Back.jpg)]]
    119
    1210All the MGT connectors are located on the north side of the FPGA Board; both on the top and bottom.
    1311
    14 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SATA.jpg)]]
    15 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_HSSDC2.jpg)]]
    16 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SFP.jpg)]]
     12=== MGT Connectors ===
     13There are three types of MGT connectors on the board. Two Small form-factor Pluggable (SFP) are connected to one column in the FPGA. The HSSDC2 and SATA interfaces are connected to the other column.
    1714
    18 === MGT Connectors ===
     15|| [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SATA.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_HSSDC2.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SFP.jpg)]] ||
     16|| '''SATA Interfaces''' || '''HSSDC2 Interfaces ''' || '''SFP Interfaces ''' ||
    1917
    20 There are three types of MGT connectors on the board. Two Small form-factor Pluggable (SFP) occupy their own column. Four HSSDC2 connectors and two SATA occupy one column.
     18The MGT interfaces are labeled "MGT 1" to "MGT 8" on the WARP FPGA board. The table below shows the mapping of each interface to the corresponding MGT in the FPGA.
    2119
    22 || '''MGT #''' || '''Type''' || '''Connector''' || '''MGT Tile''' || '''Column''' || '''LOC Constraint''' || '''TXP''' || '''TXN''' || '''RXP''' || '''RXN''' || '''Ideal Clocks''' ||
    23 || 1 || SATA Target || J47 || 112B || 1 || GT11_X1Y4 || P1 || R1 || U1 || V1 || MGTCLK_110 or MGTCLK_113 ||
    24 || 2 || SATA Host || J46 || 112A || 1 || GT11_X1Y5 || M1 || N1 || J1 || K1 || MGTCLK_110 or MGTCLK_113 ||
    25 || 3 || HSSDC2 || J3 || 113B || 1 || GT11_X1Y6 || A4 || A3 || C1 || D1 || MGTCLK_110 or MGTCLK_113 ||
    26 || 4 || HSSDC2 || J4 || 113A || 1 || GT11_X1Y7 || A6 || A5 || A9 || A8 || MGTCLK_110 or MGTCLK_113 ||
    27 || 5 || HSSDC2 || J5 || 114B || 1 || GT11_X1Y8 || A14 || A13 || A11 || A10 || MGTCLK_110 or MGTCLK_113 ||
    28 || 6 || HSSDC2 || J6 || 114A || 1 || GT11_X1Y9 || A16 || A15 || A19 || A18 || MGTCLK_110 or MGTCLK_113 ||
    29 || 7 || SFP !#1 || J49 || 102A || 0 || GT11_X0Y7 || A34 || A35 || A31 || A32 || MGTCLK_102 or MGTCLK_105 ||
    30 || 8 || SFP !#2 || J48 || 102B || 0 || GT11_X0Y6 || A36 || A37 || C39 || D39 || MGTCLK_102 or MGTCLK_105 ||
    31 
     20||'''MGT #'''||'''Type'''||'''Connector'''||'''MGT Tile'''||'''Column'''||'''LOC Constraint'''||'''TXP'''||'''TXN'''||'''RXP'''||'''RXN'''||'''Ideal Clocks'''||
     21||1||SATA Target||J47||112B||1||GT11_X1Y4||P1||R1||U1||V1||MGTCLK_110 or MGTCLK_113||
     22||2||SATA Host||J46||112A||1||GT11_X1Y5||M1||N1||J1||K1||MGTCLK_110 or MGTCLK_113||
     23||3||HSSDC2||J3||113B||1||GT11_X1Y6||A4||A3||C1||D1||MGTCLK_110 or MGTCLK_113||
     24||4||HSSDC2||J4||113A||1||GT11_X1Y7||A6||A5||A9||A8||MGTCLK_110 or MGTCLK_113||
     25||5||HSSDC2||J5||114B||1||GT11_X1Y8||A14||A13||A11||A10||MGTCLK_110 or MGTCLK_113||
     26||6||HSSDC2||J6||114A||1||GT11_X1Y9||A16||A15||A19||A18||MGTCLK_110 or MGTCLK_113||
     27||7||SFP !#1||J49||102A||0||GT11_X0Y7||A34||A35||A31||A32||MGTCLK_102 or MGTCLK_105||
     28||8||SFP !#2||J48||102B||0||GT11_X0Y6||A36||A37||C39||D39||MGTCLK_102 or MGTCLK_105||
    3229
    3330=== MGT Clocking ===
     31THe WARP FPGA Board provides very flexible MGT clocking. The Virtex-4 FPGA organizes the MGTs into two columns. Each column provides two clock inputs. Each MGT can use either clock driven into its column
     32As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.
    3433
    3534[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Clk_Blkdgm.jpg, 600px)]]
    3635
    37 As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.
    3836
    39 '''Clock Sources'''[[BR]]
    40 || '''Clock Source''' || '''Component''' || '''Mux Input ''' || '''Default Value''' ||
    41 || MGT Clk A || J14 or J11/J18 || 0 || - ||
    42 || MGT Clk B || Y2 || 1 || ??? ||
    43 || MGT Clk C || Y3 || 2 || ??? ||
    44 || MGT Clk D || Y4 || 3 || Not Installed ||
    45 || MGT Clk E || Y8 || - || 300MHZ LVDS ||
     37'''MGT Clock Sources'''[[BR]]
    4638
    47 [[BR]]
    48 '''Clock Inputs'''[[BR]]
    49 || '''Clock''' || '''Tile''' || '''LOC''' || '''P Pin''' || '''N Pin''' || '''Driver''' ||
    50 || MGTCLK_102 || 102 || GT11CLK_X0Y3 || F39 || G39 || Mux3 ||
    51 || MGTCLK_105 || 105 || GT11CLK_X0Y1 ||  AW34 || AW33 || Mux4 ||
    52 || MGTCLK_110 || 110 || GT11CLK_X1Y1 ||  AW6 || AW7 || MGT Clk E (Y8) ||
    53 || MGTCLK_113 || 113 || GT11CLK_X1Y3 ||  F1 || G1 || Mux2 ||
     39||'''Clock Source'''||'''Component'''||'''Mux Input '''||'''Source'''||
     40||MGT Clk A||J14 or J11/J18||0||Off Board Connectors||
     41||MGT Clk B||Y2||1||Oscillator (Not Installed)||
     42||MGT Clk C||Y3||2||250MHz Oscillator||
     43||MGT Clk D||Y4||3||Oscillator (Not Installed)||
     44||MGT Clk E||Y8||-||300MHz Oscillator||
    5445
     46[[BR]] '''FPGA MGT Clock Inputs'''[[BR]]
    5547
    56 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_ExtClk.jpg)]] [[BR]]
    57 '''External clock input and output (top of the FPGA Board)'''
     48||'''Clock Input'''||'''Tile'''||'''Column'''||'''GT11CLK LOC'''||'''P Pin'''||'''N Pin'''||'''Source'''||
     49||MGTCLK_102||102||0||GT11CLK_X0Y3||F39||G39||Mux 3||
     50||MGTCLK_105||105||0||GT11CLK_X0Y1||AW34||AW33||Mux 4||
     51||MGTCLK_110||110||1||GT11CLK_X1Y1||AW6||AW7||MGT Clk E (Y8)||
     52||MGTCLK_113||113||1||GT11CLK_X1Y3||F1||G1||Mux 2||
     53
     54[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_ExtClk.jpg)]] [[BR]] '''External clock input and output (top of the FPGA Board)'''
    5855
    5956There are four clock multiplexers on the board with four inputs each. The four possible inputs are MGT Clk A (external clock), MGT Clk B (NM), MGT Clk C (250 MHz) and MGT Clk D (NM). Mux1 is used to source another board, especially useful for sharing clocks between boards. The other three multiplexers source one of the FPGA Clock inputs. As there are four inputs, two bits are required to control every mux. Two 4-input dip switches choose the output of every mux.
    6057
    61 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]] [[BR]]
    62 '''Multiplexer output select switches (bottom of the FPGA Board)'''
     58[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]] [[BR]] '''Multiplexer output select switches (bottom of the FPGA Board)'''
    6359
    6460The following table details the value required for each bit of SW10 and SW11 to obtain the desired output.
    6561
    66 || || '''MGT Clk A''' || '''MGT Clk B''' || '''MGT Clk C''' || '''MGT Clk D''' || '''SW/Bit''' ||
    67 || '''Mux1''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]] || SW10, Bits 2 and 3 ||
    68 || '''Mux2''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]] || SW10, Bits 0 and 1 ||
    69 || '''Mux3''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]] || SW11, Bits 2 and 3 ||
    70 || '''Mux4''' || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]] || SW11, Bits 0 and 1 ||
     62||||'''MGT Clk A'''||'''MGT Clk B'''||'''MGT Clk C'''||'''MGT Clk D'''||'''SW/Bit'''||
     63||'''Mux1'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW10, Bits 2 and 3||
     64||'''Mux2'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW10, Bits 0 and 1||
     65||'''Mux3'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW11, Bits 2 and 3||
     66||'''Mux4'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW11, Bits 0 and 1||
    7167
    7268More information regarding MGT designs is included in Xilinx documentation ([http://www.xilinx.com/support/documentation/user_guides/ug076.pdf MGT User Guide]).
    7369
    7470=== Connectors & Cables ===
    75 
    7671Four MGTs are wired to Infiniband-keyed HSSDC2 jacks. You must use an Infiniband-keyed 100Ω HSDDC2-HSDDC2 cable to connect two FPGA boards together. One such cable is made by Molex ([http://www.molex.com/molex/products/datasheet.jsp?part=active/0739392002_CABLE_ASSEMBLIES.xml&channel=Products&Lang=en-US Molex HSDDC2 Cables]).
    7772
    7873The two SFP connectors require an additional module to connect Ethernet cables. [http://www.molex.com/molex/family/intro.jsp?superFamOID=-16821&pageTitle=Introduction&channel=Products&familyOID=-12001&chanName=family&frellink=Introduction Molex] creates one such module supported by the FPGA.
    79 
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    82 
    83