Changes between Version 25 and Version 26 of HardwareUsersGuides/FPGABoard_v2.2/MGTs


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Timestamp:
Oct 8, 2009, 2:29:51 PM (15 years ago)
Author:
murphpo
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  • HardwareUsersGuides/FPGABoard_v2.2/MGTs

    v25 v26  
    11[[TracNav(HardwareUsersGuides/FPGABoard_v2.2/TOC)]]
    22
    3 == WARP FPGA Board MGTs ==
     3= WARP FPGA Board MGTs =
    44The Virtex-4 FPGA is equipped with 10 pairs of differential multi-gigabit transceivers. Each MGT is a full-duplex transceiver supporting serial data rates up to 6.5 Gbps. The WARP FPGA board includes 8 MGT interfaces: 4 HSSDC2, 2 SATA and 2 SFP.
    55
    … …  
    1010All the MGT connectors are located on the north side of the FPGA Board; both on the top and bottom.
    1111
    12 === MGT Connectors ===
     12== MGT Interfaces ==
    1313There are three types of MGT connectors on the board. Two Small form-factor Pluggable (SFP) are connected to one column in the FPGA. The HSSDC2 and SATA interfaces are connected to the other column.
    1414
    … …  
    2828||8||SFP !#2||J48||102B||0||GT11_X0Y6||A36||A37||C39||D39||MGTCLK_102 or MGTCLK_105||
    2929
    30 === MGT Clocking ===
    31 THe WARP FPGA Board provides very flexible MGT clocking. The Virtex-4 FPGA organizes the MGTs into two columns. Each column provides two clock inputs. Each MGT can use either clock driven into its column
    32 As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.
     30== MGT Clocking ==
     31The WARP FPGA Board provides very flexible MGT clocking. The Virtex-4 FPGA organizes the MGTs into two columns. Each column provides two clock inputs. An MGT can use either clock driven into its column.
     32
     33The FPGA Board supports five MGT clock sources- four oscillators and one off-board connector. Two oscillators are installed by default; the remaining oscillator footprints can be populated as needed to support custom applications.
     34
     35One oscillator is connected directly to an FPGA MGT clock input. The remaining clock sources (four oscillators and off-board connectors) are connected to the FPGA through a flexible multiplexor network. This network allows the user to assign any of the four clock sources to any of the three FPGA MGT clock inputs. It also provides an off-board clock output which can be connected to another FPGA board, allowing multiple FPGA boards to share an MGT reference clock.
     36
     37The image and tables below provide details for the WARP FPGA Board's MGT clocking system.
    3338
    3439[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:MGT_Clk_Blkdgm.jpg, 600px)]]
    3540
    36 
    3741'''MGT Clock Sources'''[[BR]]
    38 
    3942||'''Clock Source'''||'''Component'''||'''Mux Input '''||'''Source'''||
    4043||MGT Clk A||J14 or J11/J18||0||Off Board Connectors||
    … …  
    4447||MGT Clk E||Y8||-||300MHz Oscillator||
    4548
    46 [[BR]] '''FPGA MGT Clock Inputs'''[[BR]]
    47 
     49'''FPGA MGT Clock Inputs'''[[BR]]
    4850||'''Clock Input'''||'''Tile'''||'''Column'''||'''GT11CLK LOC'''||'''P Pin'''||'''N Pin'''||'''Source'''||
    4951||MGTCLK_102||102||0||GT11CLK_X0Y3||F39||G39||Mux 3||
    … …  
    5254||MGTCLK_113||113||1||GT11CLK_X1Y3||F1||G1||Mux 2||
    5355
    54 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_ExtClk.jpg)]] [[BR]] '''External clock input and output (top of the FPGA Board)'''
     56=== MGT Clock Mux Network ===
    5557
    56 There are four clock multiplexers on the board with four inputs each. The four possible inputs are MGT Clk A (external clock), MGT Clk B (NM), MGT Clk C (250 MHz) and MGT Clk D (NM). Mux1 is used to source another board, especially useful for sharing clocks between boards. The other three multiplexers source one of the FPGA Clock inputs. As there are four inputs, two bits are required to control every mux. Two 4-input dip switches choose the output of every mux.
     58There are four clock multiplexers on the board with four inputs each. The muxes have the same four inputs: MGT Clk A (external clock), MGT Clk B, MGT Clk C and MGT Clk D. Mux1 is used to source another board, especially useful for sharing clocks between boards. The other three multiplexers source one of the FPGA Clock inputs. As there are four inputs, two bits are required to control every mux. Two 4-input dip switches choose the output of every mux.
    5759
    5860[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_SourceSelect.jpg)]] [[BR]] '''Multiplexer output select switches (bottom of the FPGA Board)'''
    … …  
    6668||'''Mux4'''||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_00.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_01.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_10.jpg)]]||[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:Dip_11.jpg)]]||SW11, Bits 0 and 1||
    6769
     70=== Off-Board MGT Clock Connections ===
     71The FPGA Board provides input and output interfaces for inter-board MGT clock connections. Each interface is composed of three connectors- 2 MMCX jacks, (for dual-coax cables) and a 4-pin 0.1" male header (for twisted pair cables). Only one cable type (either dual-coax or twisted pair) should be used per interface. The image below shows the interfaces on the FPGA Board.
     72
     73[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_ExtClk.jpg)]] [[BR]] '''External MGT clock input and output'''
     74
     75
    6876More information regarding MGT designs is included in Xilinx documentation ([http://www.xilinx.com/support/documentation/user_guides/ug076.pdf MGT User Guide]).
    6977