WARP FPGA Board MGTs

The Virtex-4 FPGA is equipped with 10 pairs of differential multi-gigabit transceivers. The MGTs can support data rates of up to 6.5 Gbps including standards such as SATA, gigabit Ethernet and Infiniband. Each of these requires a different clock speed for best performance. On the FPGA Board three different connectors have been provided: SATA host and target, HSSDC2 jacks and SFP modules.

The MGTs on the FPGA are organized in two columns. Each column has two clock inputs and all the MGTs in the column can use either of those clocks. Our design maximizes the functionality by allowing the user to select the clock frequency that is input to the columns.

All the MGT connectors are located on the north side of the FPGA Board; both on the top and bottom.

MGT Connectors

There are three types of MGT connectors on the board. Two Small form-factor Pluggable (SFP) occupy their own column. Four HSSDC2 connectors and two SATA occupy one column.

MGT #	Type	Connector	MGT Tile	Column	LOC Constraint	TXP	TXN	RXP	RXN
1	SATA Target	J47	112B	1	GT11_X1Y4	P1	R1	U1	V1
2	SATA Host	J46	112A	1	GT11_X1Y5	M1	N1	J1	K1
3	HSSDC2	J3	113B	1	GT11_X1Y6	A4	A3	C1	D1
4	HSSDC2	J4	113A	1	GT11_X1Y7	A6	A5	A9	A8
5	HSSDC2	J5	114B	1	GT11_X1Y8	A14	A13	A11	A10
6	HSSDC2	J6	114A	1	GT11_X1Y9	A16	A15	A19	A18
7	SFP #1	J49	102A	0	GT11_X0Y7	A34	A35	A31	A32
8	SFP #2	J48	102B	0	GT11_X0Y6	A36	A37	C39	D39

MGT Clocking

As mentioned, each MGT column has two input clocks that are shared. Any of the MGT tiles in that column share the clocks. In column 0 the clock inputs are located at tile 102 and tile 105. In column 1, the inputs are tile 10 and tile 13. There is an elaborate clock multiplexer scheme on the board that lets the user choose three of the four clock inputs.

Clock	Tile	P Constraint	N Constraint	Clock Frequency/Clock Mux
MGTCLK_102	102	F39	G39	Mux3
MGTCLK_105	105	AW34	AW33	Mux4
MGTCLK_110	110	AW6	AW7	300 MHz
MGTCLK_113	113	F1	G1	Mux2

External clock input and output (top of the FPGA Board)

There are four clock multiplexers on the board with four inputs each. The four possible inputs are MGT Clk A (external clock), MGT Clk B (NM), MGT Clk C (250 MHz) and MGT Clk D (NM). Mux1 is used to source another board, especially useful for sharing clocks between boards. The other three multiplexers source one of the FPGA Clock inputs. As there are four inputs, two bits are required to control every mux. Two 4-input dip switches choose the output of every mux.

Multiplexer output select switches (bottom of the FPGA Board)

The following table details the value required for each bit of SW10 and SW11 to obtain the desired output.

	MGT Clk A	MGT Clk B	MGT Clk C	MGT Clk D	SW/Bit
Mux1					SW11, Bits 0 and 1
Mux2					SW11, Bits 0 and 1
Mux3					SW11, Bits 0 and 1
Mux4					SW11, Bits 0 and 1