| Version 4 (modified by chunter, 11 years ago) (diff) |
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WARPLab 7
- Downloads
Getting Started
- Sample Buffer Sizes
- Automatic Gain Control
- Examples
- Extending WARPLab
- Debugging Errors
- Porting Code
- Benchmarks
WARPLab 7 Framework
WARPLab 7 Reference Design
Reference Design Modules
- Node
Interface Group
Baseband
Transport
Trigger Manager
Hardware
8x2 Array Example
Attachments (9)
- 8x2_overview.jpg (313.4 KB) - added by chunter 11 years ago.
- 8x2_cable_macro.jpg (374.8 KB) - added by chunter 11 years ago.
- 8x2_cable_micro.jpg (263.7 KB) - added by chunter 11 years ago.
- 8x2_result.png (208.0 KB) - added by chunter 11 years ago.
- 8x2_diagram.png (110.7 KB) - added by chunter 11 years ago.
- SIP_clock_source.png (9.7 KB) - added by chunter 9 years ago.
- SIP_clock_sink.png (9.8 KB) - added by chunter 9 years ago.
- 8x2_primary.jpg (220.5 KB) - added by chunter 8 years ago.
- 8x2_secondary.jpg (224.5 KB) - added by chunter 8 years ago.
Download all attachments as: .zip
