WARPLab 7.2.0 FPGA Architecture for WARP v3 Hardware

The WARPLab 7.2.0 design for WARP v3 makes some significant changes to the underlying FPGA architecture in order to improve performance. This includes:

• Updates to AXI interconnect to use the DC bus on the Microblaze
• Increased bus width for interconnect attached to the DC bus
• Replaced AXI FIFO with AXI DMA for Ethernet A
• Addition of DDR
• Updates to Address Map

Interconnect Architecture

Address Map